There is a case in which a screen scan in a direction opposite to that of an ordinary screen scan is required in a display apparatus. For example, such screen scan is required in a case where a liquid crystal display apparatus that employs a twisted nematic (TN) liquid crystal display panel whose lower viewing angle is small is set at a position higher than eyes of the user. In order to meet such purpose and increase availability of a liquid crystal display apparatus, it is preferable to realize a screen scan not only in a direction of an ordinary screen scan but also in the opposite direction.
In order to change a scan direction in the vertical direction in a liquid crystal display apparatus whose a scan direction is changeable, it is necessary to consider the number of extra (residual) output from a gate driver and input to the gate drive a start pulse signal (hereinafter termed “gate start pulse signal”) at an earlier timing than in the case of a scan in the ordinary direction by the number of extra outputs from the gate driver. The number of extra (residual) outputs from a gate driver means a number obtained by subtracting the number of display lines in the vertical direction of a liquid crystal display panel from the number of outputs from a gate driver that drives gate lines of the liquid crystal display panel.
Even when a scan is performed in the opposite direction, a video signal is input at the same timing as in the case where a scan is performed in an ordinary direction. Therefore, it is necessary to input a gate start pulse signal to a gate driver during a vertical blank period that precedes the input timing of the video signal. Since it is necessary to input a gate start pulse signal before a video signal for a concerned frame is input, generation timing of the gate start pulse signal should be set based on a frame previous to the concerned frame.
There is also a case in which a vertical blank period for a video signal input to a liquid crystal display apparatus varies per frame due to image processing of display data, resolution transformation and so on.
In a case where a scan is performed in an opposite direction and there is an extra output from a gate driver, if a vertical blank period varies, the position at which the gate start pulse signal is shifted from a proper position and a display error occurs. The reason is that the gate start pulse signal is generated based on the previous frame as described above.
A conventional driving method, in a case where a scan is performed from a side at which there is an extra output from a gate driver, is described with reference to the drawings. FIG. 9 is a timing chart illustrating a driving method of a conventional liquid crystal display apparatus. It is assumed that the liquid crystal display device comprises the structure as shown in FIG. 1 (described later on) except for a driving circuit 10.
With reference to FIG. 9, a gate driver clock signal VCK is input to the gate driver V-Dr also during a vertical blank period. A gate start pulse signal VSP is generated at a timing that precedes the beginning of a display frame by n multiples of the gate driver clock signal VCK, where m denotes the number of display lines in the vertical (V) direction, r denotes the number of pulses in the gate driver clock signal VCK during the vertical blank period, and n denotes the number of extra outputs from the gate driver. The gate start pulse signal VSP is generated at a timing that is located in a previous frame of the display frame and at (m+r−n+1)-th position from the beginning of the previous frame.
Since the gate start pulse signal VSP is input beforehand in this way, scan of extra outputs from the gate driver V-Dr is completed during the vertical blank period of the previous frame, and scan starts, at the beginning of the display frame, from an output (Gm) that is actually connected to a panel scan line.
However, according to this method, in a case where the vertical blank period varies per frame, the timing at which the gate start pulse signal VSP is generated deviates from the proper position and a display error occurs.
A conventional driving method, in a case where a vertical blank period varies, is described with reference to the drawings. FIG. 10 is a timing chart illustrating a driving method of a conventional liquid crystal display apparatus. FIG. 10 illustrates an operation in a case where a vertical blank period has been extended by one period of a gate driver clock signal VCK.
Since the timing at which a gate start pulse signal VSP is generated is determined based on the beginning of the previous frame, the timing becomes (m+r−n+1) even when the vertical blank period has varied. However, since the vertical blank period has been extended, the number of pulses in the gate driver clock signal VCK, from input of the gate start pulse signal VSP to the beginning of the display frame, increases by one. Therefore, scan starts from an output Gm-1 as the first line of the display frame. Therefore, in a liquid crystal display apparatus with a structure as shown in FIG. 1, the displayed image deviates toward the upper direction by one line.
Although a scan is not performed from a side at which there is an extra output from a gate driver, a method to avoid a display error caused by variation in the vertical blank period is described in Patent Document 1.
FIG. 11 is a timing chart illustrating a liquid crystal display module described in Patent Document 1. With reference to FIG. 11, when a driving circuit detects termination of a data enable signal DE that indicates start of a blanking period, a first start vertical signal STV1 and a second start vertical signal STV2 are set to an active state and kept in the state, for example, at a gate clock cycle C2 of a gate clock signal CPV. A gate-on enable signal OE is set to an enable state and kept in the state and transmission of the gate clock signal CPV is terminated at a gate clock cycle C3 of the gate clock signal CPV.
Under this condition, when the driving circuit detects a data enable signal that indicates termination of the blanking period, transmission of the gate clock signal CPV is restarted at a predetermined timing based on the data enable signal DE. The second start vertical signal STV 2 is set to an inactive state and the gate-on enable signal OE is set to a disenable state at a predetermined timing based on the gate clock signal CPV.